1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display (LCD) device, and more particularly, to a thin film transistor (TFT) array substrate and a method for fabricating the same, for an LCD device. Embodiments of the invention are suitable for a wide scope of applications. In particular, embodiments of the invention are suitable for reducing a number of exposure masks in a fabrication process of the LCD device.
2. Discussion of the Related Art
Among various flat panel display devices, an LCD device has gained great interest because it provides a high contrast ratio, wide gray scale range, displays high-quality moving images, and consumes low power. The LCD device includes various elements forming various driving patterns or lines on a substrate. Generally, these patterns of the LCD device are formed by a photolithography process.
The photolithography process involves complicated steps of coating thin film layers on a substrate with photoresist which is sensitive to ultraviolet rays; exposing and development of the substrate through an exposure mask positioned above the substrate; etching the film layer by using the patterned photoresist as a mask; and stripping the photoresist.
A TFT array substrate of a related art LCD device includes a gate line layer, a gate insulation layer, a semiconductor layer, a data line layer, a passivation layer, and a pixel electrode. Five to seven steps are generally needed to form the above-mentioned elements on the TFT array substrate. The likelihood of error increases with the number of masks used in the photolithography process. Recently, new approaches have been investigated for improving productivity and the process margin by using a reduced number of masks in the photolithography process.
FIGS. 1A to 1E show cross-sectional views of a process of fabricating a TFT array substrate according to the related art. First, as shown in FIG. 1A, a low-resistance metal material is deposited on a substrate 11 and is treated by photolithography to form a plurality of gate lines (not shown), a gate electrode 12a, and a gate pad 22. In this case, the low-resistance metal material may include copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), or chrome (Cr), etc.
The photolithography is performed as follows. First, the low-resistance metal layer is deposited on a transparent glass substrate having a good heat-resistance under a high temperature, and coated with a photoresist. Then, a first mask having a first pattern layer is positioned above the photoresist on the substrate. Light is selectively applied to the substrate through the first mask. Thus, a predetermined pattern is formed on the photoresist in accordance with the first pattern layer.
Next, a predetermined portion of the photoresist is removed by using a developer to pattern the photoresist. Light is irradiated through the predetermined portion of the photoresist on an exposed portion of the metal layer. Then, the exposed portion of the metal layer is selectively etched to obtain a desired pattern in the metal layer.
Next, as shown in FIG. 1B, an inorganic material layer is deposited on the entire surface of the substrate including the gate electrode 12a at a high temperature to form a gate insulation layer 13. In this case, the inorganic material may include silicon nitride (SiNx) or silicon oxide (SiOx). Then, an amorphous silicon layer is deposited on the gate insulation layer 13, and is then patterned by photolithography using a second mask. Accordingly, an island-shaped semiconductor layer 14 is formed on the gate insulation layer 13, wherein the semiconductor layer 14 overlaps the gate electrode 12a. 
Referring to FIG. 1C, a low-resistance metal layer is deposited on the entire surface of the substrate including the semiconductor layer 14. In this case, the low-resistance metal layer may include copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), or chrome (Cr). Then, the low-resistance metal layer is patterned by photolithography using a third mask, whereby a data line layer is formed.
The data line layer includes a data line (not shown) which perpendicular to the gate line, to thereby define a pixel region; source and drain electrodes 15a and 15b overlapped with both sides of the semiconductor layer 14; and a data pad 25 in a pad region. The deposited gate electrode 12a, gate insulation layer 13, semiconductor layer 14 and source and drain electrodes 15a and 15b form a TFT for switching on and off state a voltage applied to the pixel region.
Next, as shown in FIG. 1D, an organic insulation layer of BCB or an inorganic insulation of SiNx is formed onto the entire surface of the substrate including the drain electrode 15b to form a passivation layer 16. Then, portions of the passivation layer 16 are removed by photolithography using a fourth mask to form a contact hole 71 exposing the drain electrode 15b, a first pad open area 81a exposing the gate pad 22, and a second pad open area 81b exposing the data pad 25.
As shown in FIG. 1E, a transparent conductive material layer, for example, indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the substrate including the passivation layer 16, and is then patterned by photolithography using a fifth mask. Thus, a pixel electrode 17 is formed in the pixel region. The pixel electrode 17 is electrically connected with the drain electrode 15b, thereby completing the TFT array substrate. Then, a transparent conductive layer 27 is formed by covering the first and second pad open areas to prevent an oxidation of the gate and data pads.
Accordingly, the related art TFT array substrate requires five exposure masks to form the gate line layer, the semiconductor layer, the data line layer, the contact hole of the passivation layer, and the pixel electrode. The fabrication process becomes more complicated with the number of masks. Also fabrication time and cost increases, reducing efficiency.